This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-328057, filed Oct. 25, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a ferroelectric memory (ferroelectric random access memory) having a cell array in which a plurality of ferroelectric memory cells are arranged in a matrix format. Each memory cell includes a field-effect transistor and a capacitor formed as a gate electrode section of the field-effect transistor and having a stacked structure of metal film/ferroelectric film/metal film. Typically, this memory cell is known as a memory cell having an MFMIS (Metal/Ferroelectric/Metal/Insulator/Semiconductor) structure. This ferroelectric memory is used in an integrated circuit dedicated to a memory, a logic-in-memory integrated circuit, and the like.
2. Description of the Related Art
A ferroelectric memory as a nonvolatile memory is characterized by nondestructive read-out and generally requires no rewrite action. However, as devices are micropatterned, the device structures change, or the ferroelectric film quality deteriorates owing to limitations in the process, the polarization characteristics of a ferroelectric capacitor are disturbed in a relatively short time period and memory information is destroyed. This problem will be described in detail below.
FIG. 9 shows the sectional structure of a representative 1-transistor-xe2x80xa21-capacitor (1Txe2x80xa21C) ferroelectric memory cell.
A device isolation region 81 is formed on a silicon substrate 80. This ferroelectric memory cell has a MIS (Metal Insulator Semiconductor) transistor 82 and ferroelectric capacitor 83. The MIS transistor 82 includes impurity diffusion regions 821 as a drain and source, a channel region 822, a gate insulating film 823, and a gate electrode 824. The ferroelectric capacitor 83 includes a lower electrode 831, ferroelectric film 832, and upper electrode 833.
Interlevel insulating films 84 and 85 are formed on the substrate 80. W (tungsten) plugs 86 and 88 are formed to extend through these interlevel insulating films 84 and 85. The plug 86 connects the drain 821 of the MIS transistor and an Al (aluminum) bit line 87. The plug 88 connects the source 821 of the MIS transistor and an Al line 89. This Al line 89 connects the plug 88 to the upper electrode 833 of the ferroelectric capacitor.
This ferroelectric memory cell shown in FIG. 9 has a structure (offset structure) in which the MIS transistor 82 and ferroelectric capacitor 83 are separated in the lateral direction. Since this inevitably increases the size in the lateral direction, a problem arises from the viewpoint of high integration.
Recently, therefore, a 1-transistor (1T) ferroelectric memory cell in which a ferroelectric film is buried in the gate electrode section of a MIS transistor has been studied (T. Nakamura et al., xe2x80x9cA Single Transistor Ferroelectric Memory Cellxe2x80x9d, ISSCC 95). The structure of this 1T ferroelectric memory cell will be described in detail later with reference to embodiments of the present invention. The present inventor has found that the 1T ferroelectric memory cell has the problem that the time (retention) capable of holding memory information reduces.
According to a first aspect of the present invention, there is provided a ferroelectric semiconductor memory comprising
a cell array in which a plurality of ferroelectric memory cells are arranged in a matrix format, each memory cell including a field-effect transistor and a capacitor formed as a gate electrode section of the field-effect transistor and having a stacked structure of metal film/ferroelectric film/metal film, and
a circuit section which selectively executes a read mode, program mode, and erase mode for performing data read, programming, and erase to the memory cells, and a rewrite mode for rewriting data stored in each memory cell.
According to a second aspect of the present invention, in the rewrite mode, the circuit section successively applies a program voltage and erase voltage to a word line corresponding to a selected memory cell and, in parallel with this voltage application, causes a high-breakdown-voltage sense amplifier to amplify a voltage read out to a bit line corresponding to the selected memory cell, and feeds the amplified voltage back to the corresponding bit line.
According to a third aspect of the present invention, in the rewrite mode, the circuit section applies a read voltage to the corresponding word line to read out data in the selected memory cell to the corresponding bit line and, immediately after that, applies the program voltage and erase voltage to the corresponding word line, and feeds the readout voltage back to the corresponding bit line.